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? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7393 ? half-bridge gate drive ic fan7393 ? rev. 1.0.0 december 2009 fan7393 half-bridge gate drive ic features ? floating channel for bootstrap operation to +600v ? typically 2.5a/2.5a sourcing/sinking current driving capability ? extended allowable negative v s swing to -9.8v for signal propagation at v bs =15v ? high-side output in phase of in input signal ? 3.3v and 5v input logic compatible ? matched propagation delay for both channels ? built-in shutdown function ? built-in uvlo functions for both channels ? built-in common-mode dv/dt noise cancelling circuit ? internal 370ns minimum dead time at r dt =0 ? programmable turn-on delay control (dead-time) applications ? high-speed power mosfet and igbt gate driver ? induction heating ? high-power dc-dc converter ? synchronous step-down converter ? motor drive inverter description the fan7393 is a half-bridge, gate-drive ic with shut- down and programmable d ead-time control functions that can drive high-speed mosfets and igbts operat- ing up to +600v. it has a buffered output stage with all nmos transistors designed fo r high-pulse-current driv- ing capability and minimum cross-conduction. fairchild?s high-voltage process and common-mode noise canceling techniques provide stable operation of the high-side driver under high dv/dt noise circum- stances. an advanced level-sh ift circuit offers high-side gate driver operation up to v s =-9.8v (typical) for v bs =15v. the uvlo circuit prevents malfunction when v dd and v bs are lower than the specified threshold voltage. the high-current and low-output voltage drop feature makes this device suitable for diverse half- and full- bridge inverters; motor drive inverters, switching mode power supplies, induction heating, and high-power dc- dc converter applications. ordering information for fairchild?s definition of eco status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html . 14-sop part number package operating temperature range eco status packing method FAN7393M 14-lead, smal l outline integrated circuit (soic), non-jedec, .150 inch narrow body, 225sop -40c to +125c rohs tube FAN7393Mx tape & reel
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7393 ? rev. 1.0.0 2 fan7393 ? half-bridge gate drive ic typical appli cation diagrams figure 1. typical application circuit internal block diagram figure 2. functional block diagram +15v up to 600v pwm shutdown pwm ic control r dt d boot c boot r1 r boot lo com v b v s v dd sd in dt nc 13 nc nc ho v ss nc 12 14 11 10 9 8 2 3 1 4 7 5 6 load r2 fan7393 uvlo driver pulse generator 7 5 13 11 in v dd com v b v s r r s q driver hs(on/off) ls(on/off) dt ho lo noise canceller 6 12 v ss sd 5v 2 1 4 3 pin 8, 9, 10 and 14 are no connection r dtint 250k delay uvlo schmitt trigger input shoot though prevention dead-time { dtmin=370ns } vss/com level shift 250k
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7393 ? rev. 1.0.0 3 fan7393 ? half-bridge gate drive ic pin configuration figure 3. pin configurations (top view) pin definitions pin # name description 1 in logic input for high-side and low-side gate driver output, in-phase with ho 2sd logic input for shutdown 3v ss logic ground 4 dt dead-time control with external resistor (referenced to v ss ) 5 com ground 6 lo low-side driver return 7v dd supply voltage 8 nc no connection 9 nc no connection 10 nc no connection 11 v s high-voltage floating supply return 12 ho high-side driver output 13 v b high-side floating supply 14 nc no connection lo nc fan7393 in ho dt nc nc v dd com v b v s v ss 1 2 3 4 5 6 7 14 13 12 11 10 9 8 sd nc
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7393 ? rev. 1.0.0 4 fan7393 ? half-bridge gate drive ic absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be opera- ble above the recommended operating conditions and stressing the parts to these levels is not recommended. in addi- tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. t a =25c unless otherwise specified. notes: 1. mounted on 76.2 x 114.3 x 1.6mm pcb (fr-4 glass epoxy material). 2. refer to the following standards: jesd51-2: integral circuits thermal test method environmental conditions - natural convection, and jesd51-3: low effective thermal conductivity test board for leaded surface mount packages. 3. do not exceed maximum p d under any circumstances. recommended oper ating conditions the recommended operating conditions table defines the conditions for actual dev ice operation. recommended operating conditions are specified to ensure optimal perfor mance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. note: 4. shutdown (sd ) input is internally clamped with 5.2v. symbol characteristics min. max. unit v b high-side floating supply voltage -0.3 625.0 v v s high-side floating offset voltage v b -25 v b +0.3 v v ho high-side floating output voltage v s -0.3 v b +0.3 v v lo low-side output voltage -0.3 v dd +0.3 v v dd low-side and logic fixed supply voltage -0.3 25.0 v v in logic input voltage (in) -0.3 v dd +0.3 v v sd logic input voltage (sd )v ss 5.5 v dt programmable dead-time pin voltage -0.3 v dd +0.3 v v ss logic ground v dd -25 v dd +0.3 v dv s /dt allowable offset voltage slew rate 50 v/ns p d power dissipation (1, 2, 3) 1w ja thermal resistance 110 c/w t j junction temperature +150 c t stg storage temperature -55 +150 c symbol parameter min. max. unit v b high-side floating supply voltage v s +10 v s +20 v v s high-side floating supply offset voltage 6-v dd 600 v v ho high-side output voltage v s v b v v dd low-side and logic fixed supply voltage 10 20 v v lo low-side output voltage com v dd v v in logic input voltage (in) v ss v dd v v sd logic input voltage (sd ) (4) v ss 5v dt programmable dead-time pin voltage v ss v dd v v ss logic ground -5 +5 v t a operating ambient temperature -40 +125 c
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7393 ? rev. 1.0.0 5 fan7393 ? half-bridge gate drive ic electrical characteristics v bias (v dd , v bs )=15.0v, v ss =com=0v, dt=v ss and t a = 25c, unless otherwise specified. the v in and i in parameters are referenced to v ss /com and are applicable to the respective input leads: in and sd . the v o and i o parameters are referenced to com and are applicab le to the respective output leads: ho and lo. note: 5 these parameters guaranteed by design. symbol characteristics test condition min. typ. max. unit power supply section i qdd quiescent v dd supply current v in =0v or 5v 0.9 1.5 ma i qbs quiescent v bs supply current v in =0v or 5v 50 100 a i pdd operating v dd supply current f in =20khz, no load 1.3 1.9 ma i pbs operating v bs supply current c l =1nf, f in =20khz, rms 450 800 a i sd shutdown mode supply current sd =v ss 0.95 1.5 ma i lk offset supply leakage current v b =v s =600v 10 a bootstrapped supply section v dduv+ v bsuv+ v dd and v bs supply under-voltage positive-going threshold voltage v in =0v, v dd =v bs =sweep 8.0 9.0 10 v v dduv- v bsuv- v dd and v bs supply under-voltage negative-going threshold voltage v in =0v, v dd =v bs =sweep 7.4 8.4 9.4 v v dduvh- v bsuvh v dd and v bs supply under-voltage lockout hysteresis voltage v in =0v, v dd =v bs =sweep 0.6 v input logic section v ih logic ?1? input voltage for ho & logic ?0? for lo 2.5 v v il logic ?0? input voltage for ho & logic ?1? for lo 0.8 v i in+ logic input high bias current v in =5v, sd =0v 20 50 a i in- logic input low bias current v in =0v, sd =5v 3 a r in logic input pull-down resistance 100 250 k v sdclamp shutdown (sd ) input clamping voltage 5.0 5.5 v sd + shutdown (sd ) input positive-going threshold 2.5 v sd - shutdown (sd ) input negative-going threshold 0.8 v r psd shutdown (sd ) input pull-up resistance 100 250 k gate driver output section v oh high-level output voltage (v bias - v o ) no load 1.5 v v ol low-level output voltage no load 100 mv i o+ output high, short-circuit pulsed current (5) v ho =0v, v in =5v, pw 10s 2.0 2.5 a i o- output low, short-circuit pulsed current (5) v ho =15v,v in =0v, pw 10s 2.0 2.5 a v s allowable negative v s pin voltage for in signal propagation to ho -9.8 -7.0 v
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7393 ? rev. 1.0.0 6 fan7393 ? half-bridge gate drive ic dynamic electrical characteristics v bias (v dd , v bs )=15.0v, v ss =com=0v, c l =1000pf, dt=v ss and t a =25c, unless otherwise specified. note: 6 the turn-on propagation delay time includes dead time. symbol parameter conditions min. typ. max. unit t on turn-on propagation delay time (6) v s =0v, r dt =0 550 850 ns t off turn-off propagation delay time v s =0v 200 400 ns t sd shutdown propagation delay time 180 270 ns mt on delay matching, ho & lo turn-on 0 100 ns mt off delay matching, ho & lo turn-off 0 50 ns t r turn-on rise time v s =0v 40 60 ns t f turn-off fall time v s =0v 20 35 ns dt dead time: lo turn-o ff to ho turn-on & ho turn-off to lo turn-on r dt =0 270 370 470 ns r dt =750k 1.6 2.0 2.4 s mdt dead time matching=|dt lo-ho - dt ho-lo | r dt =0 050ns r dt =750k 0250ns
fan7393 ? half-bridge gate drive ic ? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7393 ? rev. 1.0.0 7 typical characteristics figure 4. turn-on propagation delay vs. temperature figure 5. turn-off propagation delay vs. temperature figure 6. turn-on rise time vs. temperature figure 7. turn-off fall time vs. temperature figure 8. dead time (r dt =0 ) vs. temperature figure 9. dead time matching (r dt =0 ) vs. temperature -40 -20 0 20 40 60 80 100 120 250 350 450 550 650 750 850 high-side low-side t on [ns] temperature [c] -40-20 0 20406080100120 0 50 100 150 200 250 300 350 400 high-side low-side t off [ns] temperature [c] -40 -20 0 20 40 60 80 100 120 0 10 20 30 40 50 60 high-side low-side t r [ns] temperature [c] -40 -20 0 20 40 60 80 100 120 0 10 20 30 high-side low-side t f [ns] temperature [c] -40-20 0 20406080100120 250 300 350 400 450 500 550 r dt =0 dt1 dt2 dt [ns] temperature [c] -40 -20 0 20 40 60 80 100 120 -50 -25 0 25 50 r dt =0 mdt [ns] temperature [c]
fan7393 ? half-bridge gate drive ic ? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7393 ? rev. 1.0.0 8 typical characteristics (continued) figure 10. dead time (r dt =750k ) vs. temperature figure 11. dead time matching (r dt =750k ) vs. temperature figure 12. delay matching vs. temperature figure 13. dead time vs. r dt figure 14. shutdown propagation delay vs. temperature figure 15. shutdown mode supply current vs. temperature -40 -20 0 20 40 60 80 100 120 1.6 1.8 2.0 2.2 2.4 r dt =750k dt1 dt2 dt [ s ] temperature [c] -40-20 0 20406080100120 0 50 100 150 200 250 mdt [ns] temperature [c] r dt =750k -40-20 0 20406080100120 -100 -80 -60 -40 -20 0 20 40 60 80 100 mton mtoff r dt =0 delay matching [ns] temperature [c] 0 100 200 300 400 500 600 700 250 500 750 1000 1250 1500 1750 2000 2250 dt [ ns ] rdt [ k ] -40 -20 0 20 40 60 80 100 120 90 110 130 150 170 190 210 230 250 270 high-side low-side t sd [ns] temperature [c] -40 -20 0 20 40 60 80 100 120 500 750 1000 1250 1500 i sd [ a ] temperature [c]
fan7393 ? half-bridge gate drive ic ? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7393 ? rev. 1.0.0 9 typical characteristics (continued) figure 16. quiescent v dd supply current vs. temperature figure 17. quiescent v bs supply current vs. temperature figure 18. operating v dd supply current vs. temperature figure 19. operating v bs supply current vs. temperature figure 20. v dd uvlo+ vs. temperature figure 21. v dd uvlo- vs. temperature -40 -20 0 20 40 60 80 100 120 300 500 700 900 1100 1300 1500 i qdd [ a ] temperature [c] -40 -20 0 20 40 60 80 100 120 0 20 40 60 80 100 i qbs [ a ] temperature [c] -40 -20 0 20 40 60 80 100 120 700 900 1100 1300 1500 1700 1900 i pdd [ a ] temperature [c] -40 -20 0 20 40 60 80 100 120 0 200 400 600 800 i pbs [ a ] temperature [c] -40 -20 0 20 40 60 80 100 120 8.0 8.5 9.0 9.5 10.0 v dduv+ [v] temperature [c] -40-20 0 20406080100120 7.5 8.0 8.5 9.0 9.5 v dduv- [v] temperature [c]
fan7393 ? half-bridge gate drive ic ? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7393 ? rev. 1.0.0 10 typical characteristics (continued) figure 22. v bs uvlo+ vs. temperature figure 23. v bs uvlo- vs. temperature figure 24. high-level output voltage vs. temperature figure 25. low-level output voltage vs. temperature figure 26. logic high input voltage vs. temperature figure 27. logic low input voltage vs. temperature -40 -20 0 20 40 60 80 100 120 8.0 8.5 9.0 9.5 10.0 v bsuv+ [v] temperature [c] -40-20 0 20406080100120 7.5 8.0 8.5 9.0 9.5 v bsuv- [v] temperature [c] -40-20 0 20406080100120 0.0 0.5 1.0 1.5 2.0 high-side low-side v oh [v] temperature [c] -40 -20 0 20 40 60 80 100 120 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 high-side low-side v ol [v] temperature [c] -40 -20 0 20 40 60 80 100 120 1.0 1.5 2.0 2.5 3.0 v ih [v] temperature [c] -40-20 0 20406080100120 0.5 1.0 1.5 2.0 2.5 3.0 v il [v] temperature [c]
fan7393 ? half-bridge gate drive ic ? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7393 ? rev. 1.0.0 11 typical characteristics (continued) figure 28. logic input high bias current vs. temperature figure 29. allowable negative v s voltage vs. temperature figure 30. turn-on propagation delay vs. supply voltage figure 31. turn-off propagation delay vs. supply voltage figure 32. turn-on rise time vs. supply voltage figure 33. turn-off fall time vs. supply voltage -40-20 0 20406080100120 0 10 20 30 40 50 i in+ [ a ] temperature [c] -40-20 0 20406080100120 -13 -12 -11 -10 -9 -8 -7 v s [v] temperature [c] 10 12 14 16 18 20 250 350 450 550 650 750 850 high-side low-side t on [ns] supply voltage [v] 10 12 14 16 18 20 0 50 100 150 200 250 300 350 400 high-side low-side t off [ns] supply voltage [v] 10 12 14 16 18 20 0 10 20 30 40 50 60 high-side low-side t r [ns] supply voltage [v] 10 12 14 16 18 20 0 10 20 30 high-side low-side t f [ns] supply voltage [v]
fan7393 ? half-bridge gate drive ic ? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7393 ? rev. 1.0.0 12 typical characteristics (continued) figure 34. quiescent v dd supply current vs. supply voltage figure 35. quiescent v bs supply current vs. supply voltage figure 36. high-level output voltage vs. supply voltage figure 37. low-level output voltage vs. supply voltage 10 12 14 16 18 20 300 500 700 900 1100 1300 1500 i qdd [ a ] supply voltage [v] 10 12 14 16 18 20 0 20 40 60 80 100 i qbs [ a ] supply voltage [v] 10 12 14 16 18 20 0.0 0.5 1.0 1.5 2.0 high-side low-side v oh [v] supply voltage [v] 10 12 14 16 18 20 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 high-side low-side v ol [v] supply voltage [v]
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7393 ? rev. 1.0.0 13 fan7393 ? half-bridge gate drive ic switching time definitions figure 38. switching time test circuit figure 39. input/output timing diagram figure 40. switching time waveform definition +15v sd 10 f 100nf 1nf 1nf +15v 100nf lo 10 f lo com v b v s v dd sd in dt nc 13 nc nc ho v ss nc 12 14 11 10 9 2 3 1 4 7 5 6 8 in ho lo sd dt1 dt2 dt1 dt2 dt1 shutdown shutdown dt1 dt2 in ho lo 10% 90% 50% 50% 90% 10% t off 10% 90% t f t r 10% 90% t r t f t off t on t on
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7393 ? rev. 1.0.0 14 fan7393 ? half-bridge gate drive ic figure 41. shutdown waveform definition figure 42. dead time waveform definition figure 43. delay matchi ng waveform definition 90% 50% t sd ho or lo sd mdt= dt lo-ho - dt ho-lo ho lo 10% 90% 90% 10% t off dt lo-ho dt ho-lo in 50% 50% t off 50% in(ho) 50% 90% 90% 10% 10% in(lo) mt on mt off ho lo 50% 50%
fan7393 ? half-bridge gate drive ic ? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7393 ? rev. 1.0.0 15 application information negative v s transient the bootstrap circuit has the advantage of being simple and low cost, but has some limitations. the biggest diffi- culty with this circuit is the negative voltage present at the emitter of the high-side switching device when the high-side switch is turned off in half-bridge applications. if the high-side switch, q1, turns-off while the load cur- rent is flowing to an indu ctive load; a current commuta- tion occurs from high-side switch, q1, to the diode, d2, in parallel with the low-side switch of the same inverter leg. then the negative voltage present at the emitter of the high-side switching device, just before the freewheel- ing diode, d2, starts clamping, causes load current to suddenly flow to the low-side freewheeling diode, d2, as shown in figure 44. figure 44. half-bridge application circuits this negative voltage can be trouble for the gate driver?s output stage. there is the po ssibility to develop an over- voltage condition of the bootstrap capacitor, input signal missing, and latch-up proble ms because it directly affects the source v s pin of the gate driver, as shown in figure 45. this undershoot vo ltage is called ?negative v s transient. figure 45. v s waveforms during q1 turn-off figure 46 and figure 47 show the commutation of the load current between the high-side switch, q1, and low- side freewheelling diode, d3, in same inverter leg. the parasitic inductances in the in verter circuit from the die wire bonding to the pcb tracks are jumped together in l c and l e for each igbt. when the high-side switch, q1, and low-side switch, q4, are turned on, the v s1 node is below dc+ voltage by the voltage drops associated with the power switch and the parasitic inductances of the cir- cuit due to load current is flows from q1 and q4, as shown in figure 46. when the high-side switch, q1, is turned off and q4, remained turned on, the load current to flows the low-side freewheeling diode, d3, due to the inductive load connected to v s1 , as shown in figure 47. the current flows from ground (which is connected to the com pin of the gate driver) to the load and the negative voltage present at the emitte r of the high-side switching device. in this case, the com pin of the gate driver is at a higher potential than the v s pin due to the voltage drops associ- ated with freewheeling diode, d3, and parasitic ele- ments, l c3 and l e3 . figure 46. q1 and q4 turn-on figure 47. q1 turn-off and d3 conducting q1 q3 dc+ bus v s1 i load i freewheeling q2 q4 v s2 load d1 d3 d2 d4 q1 v s freewheeling gnd gnd q1 q3 dc+ bus v s1 i load i freewheeling q2 q4 v s2 l c2 l e2 l c4 l e4 l c1 l e1 l c3 l e3 v lc1 v le1 v lc4 v le4 load d1 d3 d2 d4 q1 q3 dc+ bus v s1 i load i freewheeling q2 q4 v s2 l c2 l e2 l c4 l e4 l c1 l e1 l c3 l e3 v lc3 v le3 v lc4 v le4 d1 d3 d2 d4 load
fan7393 ? half-bridge gate drive ic ? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7393 ? rev. 1.0.0 16 the fan7393 has a negative v s transient performance curve, as shown in figure 48. figure 48. negative v s transient characteristic even though the fan7393 has been shown able to han- dle these negative v s transient conditions, it is strongly recommended that the circuit designer limit the negative v s transient as much as possible by careful pcb layout to minimize the value of parasitic elements and compo- nent use. the amplitude of negative v s voltage is pro- portional to the parasitic inductances and the turn-off speed, di/dt, of the switching device. general guidelines printed circuit board layout the layout recommended for minimized parasitic ele- ments is as follows: ? direct tracks between switches with no loops or devia- tion. ? avoid interconnect links. these can add significant inductance. ? reduce the effect of lead-inductance by lowering package height above the pcb. ? consider co-locating both power switches to reduce track length. ? to minimize noise coupling, the ground plane should not be placed under or near the high-voltage floating side. ? to reduce the em coupling and improve the power switch turn-on/off performa nce, the gate drive loops must be reduced as much as possible. placement of components the recommended selection of component is as follows: ? place a bypass capacitor between the v dd and v ss pins. a ceramic 1f capacito r is suitable for most applications. this component should be placed as close as possible to the pins to reduce parasitic ele- ments. ? the bypass capacitor from v dd to com supports both the low-side driver and bootstrap capacitor recharge. a value at least ten times higher than the bootstrap capacitor is recommended. ? the bootstrap resistor, r boot , must be considered in sizing the bootstrap resistance and the current devel- oped during initial bootstrap charge. if the resistor is needed in series with the bootstrap diode, verify that v b does not fall below com (ground). recommended use is typically 5 ~ 10 , which increases the v bs time constant. if the voltage drop of the bootstrap resistor and diode is too high or the circuit topology does not allow a sufficient charging time, a fast recovery or ultra-fast recovery diode can be used. ? the bootstrap capacitor, c boot , uses a low-esr capacitor, such as a ceramic capacitor. it is strongly recommended t hat the placement of compo- nents is as follows: ? place components tied to the floating voltage pins (v b and v s ) near the respective high-voltage portions of the device and the fan7393. nc (not connected) pins in this package maximize the distance between the high-voltage and low-voltage pins ( see figure 3 ). ? place and route for bypass capacitors and gate resis- tors as close as possible to gate drive ic. ? locate the bootstrap diode, d boot , as close as possi- ble to bootstrap capacitor, c boot . ? the bootstrap diode must use a lower forward voltage drop and minimal switching time as soon as possible for fast recovery or ultra-fast diode. 0 -10 100 200 300 400 500 600 700 800 900 1000 pulse width [ns] v s [v] -20 -30 -40 -50 -60 -70 -80 -90 -100 0
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7393 ? rev. 1.0.0 17 fan7393 ? half-bridge gate drive ic package dimensions figure 49. 14-lead, small outline integrated circuit (soic), non-jedec, .150 inch narrow body, 225sop package drawings are provided as a service to customers considering fairchil d components. drawings may change in any manner without notice. please note the revision and/or date on the draw ing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild? s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ notes: a) this drawing complies with jedec ms-012 except as noted. b) this dimension is outside the jedec ms-012 value. c) all dimensions are in millimeters. d) dimensions are exclusive of burrs, mold flash, and tie bar extrusions. e) landpattern standard: soic127p600x145-14m f) drawing file name and revision : m14crev1 7.62 #1 1.27 1.80 max 1.65 1.45 0.05min 0.10 max c 0.30 0.15 0.51 0.36 pin one indicator 6.00 8.76 8.36 7 8 14 4.15 3.75 1.27 land pattern recommendation (r0.20) detail a see detail a 0.90 0.50 (r0.10) 8 top view side view end view (0.27) 0.20 cba c b a 0.36 seating plane gage plane 1.70 1.27 5.60 0.65 b b b #1
fan7393 ? half-bridge gate drive ic ? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7393 ? rev. 1.0.0 18

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